The Apollo Lunar Module (LM) carried two on-board computers: one in the Primary Guidance & Navigation System, called the LM Guidance Computer (LGC), and one in the backup Abort Guidance System (so-called because it could be used to abort the mission if the primary system failed), called the Abort Electronics Assembly (AEA).
The LGC, essentially a clone of the Apollo Guidance Computer on the Command Module, had 2K 16-bit words of ferrite-core read/write memory and 32K words of core rope read-only memory. The AEA computer had 4K 18-bit words of ferrite-core memory, 2K in a conventional read/write arrangement, and 2K in an unusual read-only configuration.
If you are unfamiliar with how ferrite-core memory works, take a look at the Wikipedia article for an explanation, then the following description will make more sense.
The read/write portion of the AEA’s memory was configured in the usual way, with each core threaded by four wires: X-select, Y-select, sense, and inhibit. The binary state of a core was read by applying equal pulses to the X and Y drive lines for the desired bit (actually 18 of them operating in parallel). This applied a full-select current to switch the core, driving it to the ONE state. If it was previously in the ZERO state, it would flip its magnetization direction, producing a voltage pulse on the sense wire. That signal was amplified and detected indicating a stored ZERO. If the core was already in the ONE state, no flux change occurred and the absence of a sense line pulse was detected as a ONE for that bit.
This form of memory exhibits destructive readout. At the conclusion of the read operation, all selected cores have been switched to the ONE state, regardless of their previous condition. To maintain the contents of a memory address, the values just read must be rewritten back to the same location.
Writing in the AEA’s memory was accomplished by sending opposite (from the read) polarity pulses down the X and Y drive lines. This produced a full-select current in the desired core (again, 18 of them in parallel), driving it to the ZERO state of magnetization. If a bit was to be written with a ONE, a pulse equal in magnitude to the X pulse, but opposite in polarity, was simultaneously applied to the inhibit line. This effectively canceled the X line’s magnetic force and the remaining half-select Y pulse was insufficient to switch the core, so it remained in the ONE state.
This configuration of the “temporary” half (2K words) of AEA’s memory is typical practice for ferrite-core read/write memories. It’s in the “permanent” half that the design is novel.
The AEA’s “permanent” or read-only half (2K 18-bit words) was constructed using the same ferrite cores used in the read/write half, although wired somewhat differently. All cores in the permanent half were threaded by the sense and Y-select wires, just as in the read/write temporary half, but in the permanent half the inhibit wires were omitted, and the X-select wire was threaded through ONLY those cores that were to store a ZERO.
Reading the permanent storage locations worked just like the temporary locations, but note that cores storing a ONE were bypassed by the X-select wire. This meant that they always saw only half-select currents, thus never switched states, which was interpreted as a ONE (just as in the read/write locations). Locations storing a ZERO were threaded by both X- and Y-select wires and always switched from their ZERO state to the ONE state, interpreted the same as for read/write cores.
At write time, all cores threaded by both X- and Y-select wires were switched to the ZERO state. There was no inhibit wire to store ONES, but all cores that were supposed to store ONES were missing the X-select wire so could not be switched back to ZERO. The Y half-select current was not enough to cause the core magnetization to flip.
The result was a ferrite-core read/write memory with half its contents hard-wired by weaving the X-select wires around cores that were to store ONES, a design I’ve never seen anywhere else.
The read-only core planes must have been extremely difficult to wire. Normal practice for read/write ferrite-core memory in those days was to thread the fine wires through the cores using a long thin, flexible steel needle welded to the end of strands of magnet wire. For the AEA permanent half of memory, wiring for each row in a core plane would be different, depending on its contents, and the needle for the X-wire would have to be carefully wiggled past the cores for ONES, instead of through them.
Footnote: I’ve also read some of the Apollo 13 mission report and found that the AEA computer in the LM was used for guidance during most of the rocket burns needed to get the crew home safely after the tank explosion in the Service Module. That’s an amazing feat considering that the AEA had only a 2K-word program (in the “permanent” memory) and was never designed to navigate in cislunar space. The LM primary computer (LGC) would have been better suited to the task but could not be used because of its excessive power consumption (battery power was limited due to the loss of fuel cells in the Service Module).