Documentation

File Comments
Address Bus Sheet 1 Address bus display
Address Bus Sheet 2 Address entry switches
ALU Assembly Notes Construction notes for the ALU section
Arithmetic Logic Unit Sheet 1 ALU function decoding
Arithmetic Logic Unit Sheet 2 Adder control & enable
Arithmetic Logic Unit Sheet 3 Zero detect
Arithmetic Logic Unit Sheet 4 Adder
Arithmetic Logic Unit Sheet 5 Logic unit
Arithmetic Logic Unit Sheet 6 AND display & enable
Arithmetic Logic Unit Sheet 7 OR display & enable
Arithmetic Logic Unit Sheet 8 XOR display & enable
Arithmetic Logic Unit Sheet 9 NOT display & enable
Arithmetic Logic Unit Sheet 10 SHL display & enable
Arithmetic Logic Unit Sheet 11 Condition register
Arithmetic Logic Unit Sheet 12 ALU result bus & display
Auxiliary Clock Generator Clock to produce pulses for front panel operations
Auxiliary Clock Timing Chart Pulse sequences produced by auxiliary clock
Bill of Materials Parts needed to build RC-3
Cable Pin Outs Pin assignments for interconnection cables
Clock Generator Clock pulse generator
Clock Timing Chart Pulse relationships for clock generator
Control – Instruction Decoding Instruction decoder and display
Control – Instruction Fetch & Incr Control signal generation for instruction fetch and increment
Control – Load/Store Control signal generation for load and store instructions
Control – SetAB/IncXY/ALU Control signal generation for SetAB, IncXY, and ALU instructions
Control – Mov8/Mov16/Misc Control signal generation for Mov8, Mov16, and Misc instructions
Control – GoTo Control signal generation for GoTo instructions
Control – Control Display Front panel display of generated control signals
Control – Control Display Front panel display of generated control signals
Control – Control Display Front panel display of generated control signals
Control – Control Display Front panel display and generation of control signal inputs
Cross-assembler configuration file Cross-32 configuration file for RC-3
Cross-assembler test assembly Assembly listing for cross-assembler test file
Cross-assembler test source file File showing examples of allowed cross-assembler instructions
Data Bus Sheet 1 Data bus display
Data Bus Sheet 2 Data entry switches
Front Panel Connector Board Front panel connector printed circuit board as-built dimensions
Front Panel Layout 1 Front panel (top through 8U)
Front Panel Layout 2 Front panel (8U through 21U)
Front Panel Layout 3 Front panel (21U through 33U)
Front Panel Layout – ALU Dimensioned front panel layout for ALU section
Front Panel Layout – Clock Dimensioned front panel layout for Clock section
Front Panel Layout – Control Dimensioned front panel layout for Control section
Front Panel Layout – Operator Panel Dimensioned front panel layout for Operators Panel section
Front Panel Layout – Power Dimensioned front panel layout for Power section
Front Panel Layout – Registers Dimensioned front panel layout for Register section
Front Panel Operations Timing Pulse sequences for LoadAddress/Examine/Deposit
Front Panel Operations Timing Pulse sequences for ExamineNext and DepositNext
Front Panel Operations Control signal generation for front panel operations
Front Panel PCB A Front panel printed circuit board A design requirements
Front Panel PCB B Front panel printed circuit board B design requirements
Front Panel PCB B Front panel printed circuit board B design requirement
Front Panel PCB B Front panel printed circuit board B cuts & jumpers for FPops row
General Drawing Notes General notes concerning drawing interpretation
Incrementer Sheet 1 Incrementer bits 15-8
Incrementer Sheet 2 Incrementer bits 7-0
Instruction Timing 8/14 Cycles Pulse sequences for Fetch/Increment, Mov, ALU, and IncXY instructions
Instruction Timing 8/10/12 Cycles Pulse sequences for SetAB, Mov16, Misc, Load, and Store instructions
Instruction Timing 24 Cycles Pulse sequences for GoTo/SetM/Call/BC family of instructions
Interconnections Sheet 1 Logic and display interconnect cabling
Interconnections Sheet 2 Power cabling
Master Timing Chart Chart of the 19 pulses required for normal operations
Memory Sheet 1 Data bus to memory
Memory Sheet 2 Memory to data bus
Memory Sheet 3 Address bus to memory (bits 14-8), chip select & output enable control
Memory Sheet 4 Address bus to memory (bits 7-0)
Memory Sheet 5 Memory control
Memory Sheet 6 Chip interfaces
Power Sheet 1 12 VDC distribution
Power Sheet 2 AC switching, power supplies, and fans
Printer Driver Driver for Robot Printer
Printer Codes ASCII to Robot Printer print code conversion table
Printer Display Panel Physical layout for printer driver display panel
Pulse Distribution Sheet 1 Front panel display of sequencer states
Pulse Distribution Sheet 2 Generation and display of pulses P-A through P-J
Pulse Distribution Sheet 3 Generation and display of pulses P-K through P-T
Pulse Distribution Sheet 4 Display and control of abort signals
Rail Layout Relay mounting rail assignments
RC-3 Instruction Set Description of instruction set
RC-3 Instruction Set Map Op code map of RC-3 instruction set
Register A General purpose register
Register B General purpose register and input to ALU
Register C General purpose register and input to ALU
Register D General purpose register
Register INC Sheet 1 Increment register control and bits 15-8
Register INC Sheet 2 Increment register bits 7-0
Register INST Instruction register
Register J Sheet 1 Jump register control
Register J Sheet 2 Jump register bits 15-8 (J1 register)
Register J Sheet 3 Jump register bits 7-0 (J2 register)
Register M Sheet 1 Memory register control
Register M Sheet2 Memory register bits 15-8 (M1 register)
Register M Sheet3 Memory register bits 7-0 (M2 register)
Register PC Sheet 1 Program counter control and bits 15-8
Register PC Sheet 2 Program counter bits 7-0
Register XY Sheet 1 XY register control
Register XY Sheet 2 XY register bits 15-8 (X register)
Register XY Sheet 3 XY register bits 7-0 (Y register)
Relay Computer Log Construction log
Relay Connector PCB Relay connector printed circuit board design requirements
Relay layout Sheet 1 Relay layout for Clock/AuxClock
Relay layout Sheet 2 Relay layout for Sequencer
Relay layout Sheet 3 Relay layout for Control
Relay layout Sheet 4 Relay layout for registers A-D
Relay layout Sheet 5 Relay layout for register XY
Relay layout Sheet 6 Relay layout for register M
Relay layout Sheet 7 Relay layout for ALU
Relay layout Sheet 8 Relay layout for memory interface
Relay layout Sheet 9 Relay layout for register J
Relay layout Sheet 10 Relay layout for Instruction Register
Relay layout Sheet 11 Relay layout for Program Counter
Relay layout Sheet 12 Relay layout for INC register and Incrementer
Sequencer Sheet 1 Sequencer stages 0-7 and Abort8 relay
Sequencer Sheet 2 Sequencer stages 8-15 and Abort10/Abort12/Abort14 relays
Sequencer Sheet 3 Sequencer stages 16-23
Sequencer Timing Chart Sheet 1 Pulses generated by sequencer stages 0-8
Sequencer Timing Chart Sheet 2 Pulses generated by sequencer stages 9-16
Sequencer Timing Chart Sheet 3 Pulses generated by sequencer stages 17-23
Sequencer Timing Chart Sheet 4 Pulse sequences for Abort8, Abort10, and Abort12 transitions
Sequencer Timing Chart Sheet 5 Pulse sequences for Abort14 transition
System Architecture Architecture drawing, courtesy of Harry Porter
Theory of Operation Guide to understanding machine operations