RC-3 is an 8-bit computer with a 16-bit address bus. It has eight general purpose registers accessible from the 8-bit data bus, four of which can be combined in pairs for use on the 16-bit address bus, and several special-purpose registers. The 8-bit Arithmetic Logic Unit provides add, increment, and a full set of logical operations. It uses 4-pole double-throw electro-mechanical relays for logic elements, with a few semiconductor diodes used to prevent electrical back feeding on certain signal lines. A full complement of 421 indicators display internal machine state, and 134 switches allow forcing of all signals during debugging operations.
The electrical design is primarily due to Dr. Harry Porter, whose work and support for our project are gratefully acknowledged. Starting from Harry’s design (hereinafter referred to as the Harry Porter Relay Computer, or HPRC), we made a number of modifications to the instruction set:
- ALU ALU function codes for RC-3 are incremented by one, making 000 the unused function code. All others are one greater than in the HPRC instruction set.
- LOAD duplicate op-codes 94-97 have been made no-ops.
- STORE duplicate op-codes 9C-9F have been made no-ops.
- MOV16 source register code 11 now loads contents of the front panel address switches and no longer is a Halt.
- MOV16 duplicate op-codes A8-AB have been made no-ops.
- LDSW a new instruction to load the A or D register from the front panel data entry switches has been added.
- HALT the Halt instruction no longer clears the PC; it is left at the current location+1.
- HLTRL a new instruction has been added to load the PC from the front panel address switches, then Halt.
- INCXY duplicate op-codes B2-BF have been made no-ops.
- PRINT op-code B1, formerly a duplicate of INCXY, has been remapped to the Print operation.
- GOTO behavior of the c (carry) bit has been inverted; the PC is loaded if the carry bit is set instead of if it is cleared.
A feature added to RC-3 (not present in the HPRC design) is the convenience of front panel operation switches. Operators need not remember the sequence of control pulses required to perform basic operations; instead they can be performed by single switch toggles on the front panel. These functions are available:
- Load Address loads the PC with the contents of the address entry switches.
- Examine reads the memory location pointed to by the PC and stores it in the A register.
- Examine Next performs an Examine, then increments the PC (useful for reading out a program or data table in memory).
- Deposit writes the contents of the data entry switches into the memory location pointed to by the PC.
- Deposit Next performs a Deposit, then increments the PC (useful for writing a program sequentially into memory).
- Restart releases a program-generated Halt (this required turning Clock power off in the HPRC).
Other changes from the HPRC design include:
- gating relays between the data and address entry switches and their respective buses, allowing loading of their contents under program control
- key-switch controlled power to debugging switches, allowing them to be disabled during normal operation
- an auxiliary clock and pulse generator to support the front panel operation functions
- a printing output subsystem that drives an external Robot Printer device
One historical attribution is needed. The adder circuit used in the ALU of both HPRC and RC-3 was designed by Konrad Zuse for the German relay computer Z3, completed in 1941. This elegant design provides full addition, with carry, using only two relays per bit (one for each input), and unlike other adders it has no carry ripple delay.
This story continues in Mechanical Design.